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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1997 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs5396 cs5397 120 db, 96 khz audio a/d converter features l 24-bit conversion l 120 db dynamic range (a-weighted) l low noise and distortion >105 db thd + n l complete cmos stereo a/d system delta-sigma a/d converters digital anti-alias filtering s/h circuitry and voltage reference l cs5396 - digital filter optimized for audio l cs5397 - non-aliasing digital filter l adjustable system sampling rates including 32, 44.1, 48 & 96 khz l differential analog architecture l linear phase digital anti-alias filtering l 10 tap programmable psychoacoustic noise shaping filter l single +5 v power supply general description the cs5396 and cs5397 are complete analog-to-digital converters for stereo digital audio systems. they per- form sampling, analog-to-digital conversion and anti- alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 100 khz per channel. the cs5396/97 use a patented 7th-order, tri-level delta- sigma modulator followed by digital filtering and decima- tion, which removes the need for an external anti-alias filter. the adcs use a differential architecture which pro- vides excellent noise rejection. the cs5396 has a linear phase filter optimized for audio applications with 0.005 db passband ripple and >117 db stopband rejection. the cs5397 has a non- aliasing filter response with 0.005 passband ripple and >117 db stopband attenuation. other features available in both the cs5396 and cs5397 are an optional low group delay filter and a unique psychoacoustic noise shaping filter which subjectively truncates the output to 16, 18 or 20 bits while 24-bit sound quality is preserved. the cs5396/97 are targeted for the highest perfor- mance professional audio systems requiring wide dynamic range, negligible distortion and low noise. ordering information cs5396-ks -10 to 50 c 28-pin soic cs5397-ks -10 to 50 c 28-pin soic CDB5396/97 evaluation board voltage reference serial output interface psychoacoustic digital decimation lp filter dac - + - + s/h lp filter dac - + - + s/h ainr+ va sclk sdata1 mclkd cs vcom mclka lrck adctl lgnd tst0 ainr- comparator comparator ainl+ ainl- vref cdin cclk agnd1 agnd2 agnd0 vl tst1 vd dgnd calibration microcontroller calibration sram dactl filter filter (with low group delay options) digital decimation filter (with low group delay options) serial control port cal sdata2 sep 97 ds229pp2
cs5396 cs5397 2 ds229pp2 table of contents table of contents.......................................................................................................2 analog characteristics ..........................................................................................4 digital filter characteristics ..............................................................................5 power and thermal characteristics .................................................................6 digital characteristics............................................................................................6 absolute maximum ratings......................................................................................6 recommended operating conditions ..................................................................7 switching characteristics .....................................................................................7 spi control port switching characteristics.................................................9 i2c control port switching characteristics ...............................................10 general description ...............................................................................................12 stand-alone vs. control port mode ........................................................................12 stand-alone mode ....................................................................................................12 master clock - stand-alone mode ..........................................................................12 serial data interface - stand-alone mode ..............................................................12 serial data- stand-alone mode .......................................................................13 serial clock - stand-alone mode ....................................................................13 left/right clock - stand-alone mode ..............................................................13 master mode - stand-alone mode ..........................................................................13 slave mode - stand-alone mode ............................................................................13 high pass filter - stand-alone mode .....................................................................13 power-up and calibration - stand-alone mode ......................................................13 synchronization of multiple devices - stand alone mode ......................................14 control port mode ..................................................................................................14 access to control port mode ..................................................................................14 internal power-on reset .................................................................................14 master clock - control port mode ..........................................................................15 64 vs. 128 oversampling modes ........................................................................15 serial data interface - control port mode ..............................................................15 serial data - control port mode ......................................................................15 serial clock - control port mode .....................................................................15 left/right clock -control port mode ................................................................15 master mode- control port mode ...........................................................................17 slave mode - control port mode ............................................................................17 synchronization of multiple devices - control port mode ......................................17 power-up and calibration - control port mode .......................................................17 high pass filter -control port mode .......................................................................17 input level monitoring - control port mode ............................................................18 high resolution mode .....................................................................................18 bar graph mode ..............................................................................................18 dual digital audio outputs .....................................................................................18 psychoacoustic filter ..............................................................................................19 low group delay filter ...........................................................................................19 c interface formats ..............................................................................................19 spi mode .........................................................................................................19 i 2 c mode .........................................................................................................19 establishing the chip address in i 2 c mode ....................................................19 analog connections - all modes .......................................................................19 grounding and power supply decoupling - all modes ............................20 digital filter plots .................................................................................................21 register description ...............................................................................................25 pin descriptions .........................................................................................................31 power supply connections .....................................................................................31 analog inputs...........................................................................................................31 analog outputs........................................................................................................32 digital inputs............................................................................................................32
cs5396 cs5397 ds229pp2 3 digital input pin definitions for stand-alone mode ............................................... 32 digital pin definitions for control-port mode................................................ 33 digital outputs......................................................................................................... 33 digital inputs or outputs.......................................................................................... 34 miscellaneous ......................................................................................................... 34 parameter definitions............................................................................................. 35 additional information........................................................................................... 36 package dimensions ................................................................................................. 37
cs5396 cs5397 4 ds229pp2 analog characteristics (t a = 25c; va, vl,vd = 5v; full-scale input sinewave, 997 hz; analog connections as shown in figure 1; measurement bandwidth is 20 hz to 20 khz unless otherwise specified; logic 0 = 0v, logic 1 = vd; notes: 1. referenced to typical full-scale differential input voltage (4.0 vpp). 2. specified for a fully differential input {(ainr+)-(ainr-)}.the adc accepts input voltages up to the analog supplies (va and agnd). full-scale outputs will be produced for differential inputs beyond vin. * refer to parameter definitions at the end of this data sheet. specifications are subject to change without notice. parameter symbol min typ max units dynamic performance dynamic range mclk equal to 24.576 mhz fs = 48 khz in 128x oversampling mode (a-weighted) fs = 48 khz in 128x mode fs = 96 khz in 64x mode (a-weighted) fs = 96 khz in 64x mode (40 khz bandwidth) mclk equal to 12.288 mhz fs = 48 khz in 64x mode (a-weighted) fs = 48 khz in 64x mode tbd tbd tbd tbd tbd tbd 120 117 120 114 117 114 - - - - - - db db db db db db total harmonic distortion + noise fs = 48 khz in 128x mode -1 db (note 1) -20 db (note 1) -60 db (note 1) fs = 96 khz in 64x mode -1 db (note 1) (40 khz bandwidth) -20 db (note 1) -60 db (note 1) fs = 48 khz in 64x mode -1 db (note 1) -20 db (note 1) -60 db (note 1) thd+n tbd tbd tbd tbd tbd tbd tbd tbd tbd 105 97 57 105 97 57 105 97 57 - - - - - - - - - db db db db db db db db db total harmonic distortion -1 db (note 1) thd tbd 0.00056 - % interchannel phase deviation - 0.0001 - deg interchannel isolation - 120 - db dynamic range performance drift (following calibration) - 0.05 - db/c dc accuracy interchannel gain mismatch - 0.05 - db gain error - 5tbd% gain drift - 100 - ppm/ c offset error (with high pass filter enabled) - 0 - lsb analog input full-scale differential input voltage (note 2) v in tbd 4 tbd v pp input impedance differential common-mode z in - - 4.5 tbd - - k w k w common-mode rejection ratio cmrr - 82 - db
cs5396 cs5397 ds229pp2 5 digital filter characteristics (t a = 25 c; va, vl,vd = 5v 5%; fs = 48 khz) notes: 3. response shown is for fs equal to 48 khz. filter characteristics scale with fs. parameter cs5396 cs5397 symbol min typ max min typ max unit high-performance filter passband(-0.01 db) 0 - 0.4604 0 - 0.3958 fs passband ripple - - 0.005 - - 0.005 db stopband 0.5542 - 63.45 0.4979 - 63.50 fs stopband attenuation 117 - - 117 - - db group delay (fs = output sample rate) 128x oversampling mode 64x oversampling mode t gd - - 34/fs 34/fs - - - - 34/fs 34/fs - - m s m s group delay variation vs. frequency d t gd --0.0--0.0 m s low group delay filter passband(-0.01 db) 128x oversampling mode 64x oversampling mode 0 0 - - 0.375 0.188 0 0 - - 0.375 0.188 fs fs passband ripple - - 0.015 - - 0.015 db stopband 128x oversampling mode 64x oversampling mode 0.646 0.323 - - 127.35 63.68 0.646 0.323 - - 127.35 63.68 fs fs stopband attenuation 86 - 86 - db group delay (fs = output sample rate) t gd - 10/fs - - 10/fs - m s group delay variation vs. frequency d t gd --0.0--0.0 m s high pass filter characteristics frequency response-3.0 db (note 3) -0.036 db (note 3) -1.8 20 - - -1.8 20 - - hz hz phase deviation@ 20hz (note 3) - 5.3 - - 5.3 - deg passband ripple - - 0 - - 0 db
cs5396 cs5397 6 ds229pp2 power and thermal characteristics (t a = 25 c; va, vl,vd = 5v5%; fs = 48 khz; master mode) digital characteristics (t a = 25 c; va, vl,vd = 5v 5%) absolute maximum ratings (agnd, dgnd = 0v, all voltages with respect to ground.) notes: 4. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 5. the maximum over/under voltage is limited by the input current. 6. applies to normal operation. greater differences during power up/down will not cause scr latch-up. warning: operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter 64x oversampling mclk=12.288 mhz 128x oversampling mclk=24.576 mhz symbol min typ max min typ max unit power supply current va+vl (normal operation) vd i a i d - - 150 65 tbd tbd - - 160 125 tbd tbd ma ma power supply current va+vl (power-down mode) vd i a i d - - 2 2 - - - - 3 3.5 - - ma ma power consumption(normal operation) (power-down mode) - - 1075 20 tbd - - - 1425 33 tbd - mw mw power supply rejection ratio (1 khz) psrr - 65 - - 65 - db allowable junction temperature - - 135 - - 135 c junction to ambient thermal impedance t ja -45- -45- c/w parameter symbol min typ max units high-level input voltage v ih 2.4 - - v low-level input voltage v il --0.8v high-level output voltage at i o = -20 m av oh vd - 1.0 - - v low-level output voltage at i o = 20 m av ol --0.4v input leakage current i in -- 10 m a parameter symbol min typ max units dc power supplies: analog logic digital |va - vd| (note 6) |va - vl| (note 6) |vd - vl| (note 6) va vl vd -0.3 -0.3 -0.3 - - - - - - - - - +6.0 +6.0 +6.0 0.4 0.4 0.4 v v v v v v input current (note 4) i in -- 10 ma analog input voltage (note 5) v in agnd-0.7 - va+0.7 v digital input voltage (note 5) v ind -0.3 - vd+0.7 v ambient operating temperature (power applied) t a -55 - +50 c storage temperature t stg -65 - +150 c
cs5396 cs5397 ds229pp2 7 recommended operating conditions (agnd, dgnd = 0v, all voltages with respect to ground.) specifications are subject to change without notice. switching characteristics (t a = 25 c; va = 5v 5%; inputs: logic 0 = 0v, logic 1 = va = vd; c l = 20 pf) parameter symbol min typ max units dc power supplies: positive digital positive logic positive analog |va - vd| (note 6) vd vl va 4.75 4.75 4.75 - 5.0 5.0 5.0 - 5.25 5.25 5.25 0.4 v v v v ambient operating temperature (power applied) t a -10 - +50 c parameter symbol min typ max units output sample rate fs 2 - 100 khz mclk period t clkw 39.06 - 1950 ns mclk low t clkl 26 - - ns mclk high t clkh 26 - - ns mclk fall time t clkft --8ns master mode sclk falling to lrck t mslr -20 - +20 ns sclk falling to sdata valid t sdo - - 20 ns sclk duty cycle - 50 - % slave mode lrck period 1/fs 10 - 500 m s lrck duty cycle - 50 - % sclk period t sclkw 4 x t clw --ns sclk pulse width low t sclkl 2 x t clw --ns sclk pulse width high t clkh 60 - - ns sclk falling to sdata valid t dss --t clw + 20 ns ns lrck edge to msb valid t lrdss --t clw + 20 ns ns sclk rising to lrck edge delay t slr1 t clw + 20 ns - - ns lrck edge to rising sclk setup time t slr2 t clw + 20 ns - - ns
cs5396 cs5397 8 ds229pp2 sclk output t mslr sdata t sdo lrck output msb msb-1 sclk to sdata & lrck - master mode serial data format, left justified sclk output t mslr sdata t sdo lrck output msb sclk to sdata & lrck - master mode serial data format, i 2 s compatible sdata sclk input lrck input sclkl t dss t msb msb-1 msb-2 lrdss t sclkh t slr1 t slr2 t t sclkw sclk to lrck & sdata - slave mode serial data format, left justified sdata sclk input lrck input sclkl t dss t msb msb-1 sclkh t slr1 t slr2 t t sclkw sclk to lrck & sdata - slave mode serial data format, i 2 s compatible
cs5396 cs5397 ds229pp2 9 spi control port switching characteristics (t a = 25 c; vd, va = 5v 5%; inputs: logic 0 = dgnd, logic 1 = vd; c l = 20 pf) notes: 7. data must be held for sufficient time to bridge the transition time of cclk. 8. for f sck < 1 mhz. parameter symbol min max unit spi mode cclk clock frequency f sck -6mhz cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 7) t dh 15 - ns rise time of cclk and cdin (note 8) t r2 -100ns fall time of cclk and cdin (note 8) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh
cs5396 cs5397 10 ds229pp2 i 2 c control port switching characteristics (t a = 25 c; vd, va = 5v 5%; inputs: logic 0 = dgnd, logic 1 = vd; c l = 20 pf) notes: 9. use of the i 2 c ? bus interface requires a license from philips. 10. data must be held for sufficient time to bridge the 300 ns transition time of scl. parameter symbol min max unit i 2 c ? mode (note 9) cclk clock frequency f scl -100khz bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s cdin hold time from cclk falling (note 10) t hdd 0-s cdin setup time to cclk rising t sud 250 - ns rise time of both cdin and cclk lines t r -1s fall time of both cdin and cclk lines t f -300ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated cdin cclk
cs5396 cs5397 ds229pp2 11 audio data processor vref ainl+ ainl- tsto1 tsto2 vd 6.8nf 0.1 m f left analog input - left analog input + a/d converter sclk sdata2 cs5396/7 cdin/dfs cclk/sm timing logic & clock mclka ainr+ right analog input - ainr- right analog input + vcom 470 m f + lrck tsto pins should be left floating, with no trace attached 39 w cs/pdn m -controller/ configuration adctl dactl va vl +5v analog 1 m f 0.1 m f +5v digital 5 w 0.1 m f 0.1 m f 1 m f + + 100 m f + 0.1 m f sdata1 agnd1 lgnd dgnd agnd2 3 12 28 25 21 8 6 9 20 7 14 13 15 17 18 19 11 23 24 1 2 4 5 27 26 39 w 39 w 39 w 6.8nf mclkd agnd0 22 16 cal 10 figure 1. typical connection diagram
cs5396 cs5397 12 ds229pp2 general description the cs5396/97 is a 24-bit, stereo a/d converter designed for stereo digital audio applications. the analog input channels are simultaneously sampled by separate, patented, 7th-order tri-level delta-sig- ma modulators at either 128 or 64 times the output sample rate (64 fs or 128 fs) of the device. the resulting serial bit streams are digitally filtered, yielding pairs of 24-bit values at output sample rates (fs) of up to 100 khz. this technique yields nearly ideal conversion performance independent of input frequency and amplitude. the converter does not require difficult-to-design or expensive anti-alias filters, and it does not require external sample-and-hold amplifiers or voltage references. only normal power supply decoupling compo- nents, voltage reference bypass capacitors and a single resistor and capacitor on each input for anti- aliasing are required, as shown in figure 1. an on- chip voltage reference provides for a differential input signal range of 4.0 vpp. the device also con- tains a high pass filter, implemented digitally after the decimation filter, to completely eliminate any internal offsets in the converter or any offsets present at the input circuitry to the device. output data is available in serial form, coded as 2's com- plement 24-bit numbers. for more information on delta-sigma modulation techniques see the refer- ences at the end of this data sheet. stand-alone vs. control port mode the cs5396/97 can operate in either stand-alone or control port mode. the functionality of pins 17, 18 and 19 is established upon entering either the stand-alone or control port mode, as described in the pin description section. the control port mode requires a micro-controller and allows access to many additional features, which include: ? 128 oversampling mode ? reduction of 24-bit data to 20, 18 or 16-bit data with psychoacoustically optimized dither ? programmability of psychoacoustic filter coef- ficients ? peak input signal level monitor with either high resolution or bar graph mode selection ? signal inversion ? high pass filter defeat ? mute ? access to the digital filter to allow the input of external digital audio data to produce a two-to- one decimated output and/or psychoacoustic bit reduction. stand-alone mode master clock - stand-alone mode the master clock is the clock source for the delta- sigma modulator sampling (mclka) and digital filters (mclkd). the required mclka/d fre- quency is determined by the desired fs and must be 256 fs. table 1 shows some common master clock frequencies. table 1. common clock frequencies for stand-alone mode serial data interface - stand-alone mode the cs5396/97 supports two serial data formats which are selected via the digital format select pin, dfs. the digital output format determines the rela- tionship between the serial data, left/right clock and serial clock. figures 2 and 3 detail the interface for- lrck (khz) mclka/d (mhz) sclk (mhz) 32 8.192 2.048 44.1 11.2896 2.822 48 12.288 3.072 64 16.384 4.096 88.2 22.5792 5.6448 96 24.576 6.144
cs5396 cs5397 ds229pp2 13 mats. the serial data interface is accomplished via the serial data outputs; sdata1 and sdata2; se- rial data clock, sclk, and the left/right clock, lrck. the serial nature of the output data results in the left and right data words being read at differ- ent times. however, the samples within an lrck cycle represent simultaneously sampled analog in- puts. serial data- stand-alone mode the serial data block consists of 24 bits of audio data presented in 2's-complement format with the msb-first. the data is clocked from sdata1 and sdata2 by the serial clock and the channel is de- termined by the left/right clock. the full precision 24-bit data is available on sdata1 and the output from the low group delay filter is available on sdata2. serial clock - stand-alone mode the serial clock shifts the digitized audio data from the internal data registers via the sdata1 and sdata2 pins. sclk is an output in master mode where internal dividers will divide the master clock by 4 to generate a serial clock which is 64 fs. in slave mode, sclk is an input with a serial clock typically between 48 and 128 fs. however, it is recommended that sclk be equal to 64 , though other frequencies are possible, to avoid potential interference effects which may degrade system per- formance. left/right clock - stand-alone mode the left/right clock, lrck, determines which channel, left or right, is to be output on sdata1 and sdata2. in master mode, lrck is an output whose frequency is equal to fs. in slave mode, lrck is an input whose frequency must be equal to fs and synchronous to mclka/d. master mode - stand-alone mode in master mode, sclk and lrck are outputs which are internally derived from the master clock. internal dividers will divide mclka/d by 4 to generate a sclk which is 64 fs and by 256 to generate a lrck which is equal to fs. the cs5396/97 is placed in the master mode with the slave/master pin, s/m , low. slave mode - stand-alone mode lrck and sclk become inputs in slave mode. lrck must be externally derived from mclka/d and be equal to fs. it is recommended that sclk be equal to 64 . other frequencies between 48 and 128 fs are possible but may degrade system performance due to interference effects. the mas- ter clock frequency must be 256 fs. the cs5396/97 is placed in the slave mode with the slave/master pin, s/m , high. high pass filter - stand-alone mode the cs5396/97 includes a high pass filter after the decimator to remove the dc offsets introduced by the analog buffer stage and the cs5396/97 analog modulator. the characteristics of this first-order high pass filter are outlined below, for fs equal to 48 khz. this filter response scales linearly with sample rate. frequency response: -3 db @ 1.8 hz -0.036 db @ 20 hz phase deviation: 5.3 degrees @ 20 hz passband ripple: none power-up and calibration - stand-alone mode the delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by exit- ing the power-down mode. however, the voltage reference will take a much longer time to reach a fi- nal value due to the presence of external capaci- tance on the vref pin. a time delay of approximately 10ms/ m f is required after applying power to the device or after exiting a power down state.
cs5396 cs5397 14 ds229pp2 a calibration of the tri-level delta-sigma modulator should always be initiated following power-up and after allowing sufficient time for the voltage on the external vref capacitor to settle. this is required to minimize noise and distortion. it is also advised that the cs5396/97 be calibrated after the device has reached thermal equilibrium, approximately 10 seconds, to maximize performance. synchronization of multiple devices - stand alone mode in systems where multiple adcs are required, care must be taken to achieve simultaneous sampling. it is recommended that the rising edge of the cal signal be timed with a falling edge of mclk to en- sure that all devices will initiate a calibration and synchronization sequence on the same rising edge of mclk. the absence of re-timing of the cal signal can result in a sampling difference of one mclk period. control port mode access to control port mode the mode selection between stand-alone and con- trol port mode is determined by the state of the sdata1 pin 250 mclk cycles following the in- ternal power-on reset. a 47 k w pull-up resistor on sdata1 will select the control port mode. how- ever, the control port will not respond to cclk and cdin until the pull-up on the sdata1 pin is re- leased. internal power-on reset the timing required to determine control port mode and i 2 s/spi mode is based on an internal power-on reset. the internal power-on reset re- quires the power supply to exceed a threshold volt- age. however, there is no external indication of when the internal reset is activated. if precise tim- ing of the control port and i 2 s/spi decisions is re- quired, mclk should not be applied until the power supply has stabilized. sdata 23 22 7 6 23 22 sclk lrck 23 22 master 24-bit left justified data data valid on rising edge of 64x sclk mclk equal to 256x fs 54 32 10 8 slave 24-bit left justified data data valid on rising edge of sclk mclk equal to 256x fs 9 76 54 32 10 8 9 left right figure 2. serial data format 0, stand-alone mode, dfs low. left justified. sdata 23 22 8 7 23 22 sclk lrck 23 22 master i s 24-bit data data valid on rising edge of 64x sclk mclk equal to 256x fs 2 slave i s 24-bit data data valid on rising edge of sclk mclk equal to 256x fs 2 65 43 21 0 87 65 43 21 0 9 9 left right figure 3. serial data format 1, stand-alone mode, dfs high. i 2 s compatible
cs5396 cs5397 ds229pp2 15 master clock - control port mode the master clock is the clock source for the delta- sigma modulator sampling (mclka) and digital filters (mclkd). the required mclka/d fre- quency is determined by the desired fs and the cho- sen oversampling mode. table 2 shows some common master clock frequencies. 64 vs. 128 oversampling modes the cs5396/97 can operate in a 64 oversampling mode with a 256 master clock (mclka/d) at a maximum sample rate of 100 khz. the device can also operate in a 128 oversampling mode with a 512 master clock (mclka/d) where the maxi- mum fs is 50 khz. notice that the required master clock is 24.576 mhz for fs equal to either 48 khz in the 128 oversampling mode or 96 khz in the 64 oversampling mode. the sampling mode is set via the control register which alters the decima- tion ratio of the digital filter. the 64 oversam- pling mode is the default mode. table 2 shows some common clock frequencies for both modes. refer to appendix a for additional discussion of 64 vs. 128 oversampling modes. table 2. common clock frequencies serial data interface - control port mode the cs5396/97 supports two serial data formats which are selected via the control register. the dig- ital output format determines the relationship be- tween the serial data, left/right clock and serial clock. figures 4 - 7 detail the interface formats. the serial data interface is accomplished via the se- rial data outputs; sdata1 and sdata2, serial data clock, sclk, and the left/right clock, lrck. the serial nature of the output data results in the left and right data words being read at different times. however, the samples within an lrck cycle repre- sent simultaneously sampled analog inputs. serial data - control port mode the serial data block is presented in 2's-comple- ment format with the msb-first. the data is clocked from sdata1 and sdata2 by the serial clock and the channel is determined by the left/right clock. the full precision 24 bit data is available on sdata1 and the output from the low group delay is available on sdata2. the serial data can be followed by 8 peak signal level, psl, bits as shown in figures 4 - 7 if the pken bit is set. refer to the dual audio output section of this data sheet for further discussion of sdata1 and sdata2 options. serial clock - control port mode the serial clock shifts the digitized audio data from the internal data registers via sdata1 and sdata2. sclk is an output in master mode where internal dividers will divide the master clock by 4 to generate a serial clock which is 64 fs in the 64 oversampling mode. in the 128 over- sampling mode, internal dividers will divide mclka/d by 4 to generate a sclk which is 128 fs. in slave mode, sclk is an input with a serial clock typically between 48 and 128 fs. it is rec- ommended that sclk be equal to 64 in the 64 oversampling mode and equal to 128 in the 128 oversampling mode to avoid possible system per- formance degradation due to interference effects. left/right clock -control port mode the left/right clock, lrck, determines which channel, left or right, is to be output on sdata1 lrck (khz) over- sampling mclka/d (mhz) sclk (mhz) 32 64 8.192 2.048 44.1 64 11.2896 2.822 48 64 12.288 3.072 32 128 16.384 4.096 44.1 128 22.5792 5.6448 48 128 24.576 6.144 64 64 16.384 4.096 88.2 64 22.5792 5.6448 96 64 24.576 6.144
cs5396 cs5397 16 ds229pp2 sdata p1 p0 24 23 9 p7 p6 p5 p4 p3 p2 8 24 23 sclk lrck p1 p0 24 23 9 p7 p6 p5 p4 p3 p2 8 master 24-bit left justified data data valid on rising edge of 64x sclk mclk equal to 256x fs slave 24-bit left justified data data valid on rising edge of sclk mclk equal to 256x fs 10 32 54 76 76 54 32 10 left right figure 4. control port mode, serial data. left justified. 64x oversampling mode the peak signal level bits are available only if bit 6 of byte 7 is set. sclk lrck master i s 24-bit data data valid on rising edge of 64x sclk mclk equal to 256x fs 2 slave i s 24-bit data data valid on rising edge of sclk mclk equal to 256x fs 2 sdata p1 p0 24 23 9 p7 p6 p5 p4 p3 p2 8 24 23 p1 p0 24 23 9 p7 p6 p5 p4 p3 p2 8 10 32 54 76 76 54 32 10 left right figure 5. control port mode, serial data. i 2 s compatible. 64x oversampling mode. the peak signal level bits are available only if bit 6 of byte 7 is set. sdata p1 p0 23 22 p7 p6 p5 p4 p3 p2 sclk lrck 23 22 master 24-bit left justified data data valid on rising edge of 128x sclk mclk equal to 512x fs slave 24-bit left justified data data valid on rising edge of sclk mclk equal to 512x fs 10 p1 p0 p7 p6 p5 p4 p3 p2 23 22 10 left right figure 6. control port mode, serial data. left justified. 128x oversampling mode the peak signal level bits are available only if bit 6 of byte 7 is set. sdata p1 p0 23 22 p7 p6 p5 p4 p3 p2 sclk 23 22 10 p1 p0 p7 p6 p5 p4 p3 p2 23 22 10 lrck master i s 24-bit data data valid on rising edge of 128x sclk mclk equal to 512x fs 2 slave i s 24-bit data data valid on rising edge of sclk mclk equal to 512x fs 2 left right figure 7. control port mode, serial data. i 2 s compatible. 128x oversampling mode. the peak signal level bits are available only if bit 6 of byte 7 is set.
cs5396 cs5397 ds229pp2 17 and sdata2. in master mode, lrck is an output whose frequency is equal to fs. in slave mode, lrck is an input whose frequency must be equal to fs and synchronous to mclka/d. master mode- control port mode in master mode, sclk and lrck are outputs which are internally derived from the master clock. in the 64 oversampling mode, internal dividers will divide mclka/d by 4 to generate a sclk which is 64 fs and by 256 to generate a lrck which is equal to fs. in the 128 oversampling mode, internal dividers will divide mclka/d by 4 to generate a sclk which is 128 fs and by 512 to generate a lrck which is equal to fs. the cs5396/97 is placed in the master mode via the control register. slave mode - control port mode lrck and sclk become inputs in slave mode. lrck must be externally derived from mclka/d and be equal to fs. it is recommended that sclk be equal to 64 in the 64 oversampling mode and equal to 128 in the 128 oversampling mode. other frequencies are possible but may degrade system performance due to interference effects. the cs5396/97 is placed in the slave mode via the control register. synchronization of multiple devices - control port mode in systems where multiple adcs are required, care must be taken to achieve simultaneous sampling. the fstart bit in register 1 controls the synchro- nization of the internal clocks and sampling pro- cess between the analog modulator and the digital filter. multiple adcs can be synchronized if the fstart command is initiated on the same edge of mclk. this can be accomplished by re-timing the cclk clock with the falling edge of mclk. this is a relatively simple matter if the adcs have the same address. however, if the system requires the devices to have individual addresses, synchroniza- tion can be accomplished by; 1) disable the address enable bit (addren) in register 7 2) issue a system broadcast fstart command synchronized with cclk. 3) reset the addren bit. power-up and calibration - control port mode the delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by exit- ing the power-down mode. however, the voltage reference will take a much longer time to reach a fi- nal value due to the presence of external capaci- tance on the vref pin. a time delay of approximately 10ms/ m f is required after applying power to the device or after exiting a power down state. a calibration of the tri-level delta-sigma modulator should always be initiated following power-up and after allowing sufficient time for the voltage on the external vref capacitor to settle. this is required to minimize noise and distortion. it is also advised that the cs5396/97 be calibrated after the device has reached thermal equilibrium to maximize per- formance. a calibration sequence requires the fol- lowing commands; 1) set the fstart bit 2) set the gnd cal bit 3) set the cal bit 4) wait a minimum of 2050 lrck periods in the 128x mode or 4100 lrck periods in the 64x mode. 5) remove gnd cal high pass filter -control port mode the cs5396/97 includes a high pass filter after the decimator to remove the dc offsets introduced by
cs5396 cs5397 18 ds229pp2 the analog buffer stage and the cs5396/97 analog modulator. the high pass filter can be defeated with the control register. it is also possible to write to the left/right offset registers to establish a prede- termined offset. the characteristics of this first-order high pass fil- ter are outlined below for fs equal to 48 khz. the filter response scales linearly with sample rate. frequency response: -3 db @ 1.8 hz -0.036 db @ 20 hz phase deviation: 5.3 degrees @ 20 hz passband ripple: none input level monitoring - control port mode the cs5396/97 includes independent peak input level monitoring for each channel. the analog-to- digital converter continually monitors the peak dig- ital signal for both channels and records these val- ues in the active registers. this information can be transferred to the output registers by writing the pu (peak update) bit which will also reset the ac- tive register. the active register contains the peak signal level since the previous peak update request. the 8-bit contents of the output registers are avail- able in both interface modes. the peak signal level information is available in two formats - high res- olution mode and bar graph mode. the output for- mat is controlled via the control register. high resolution mode bits p7-p0 indicate the peak signal level (psl) since the previous peak update (or previous write of the pu bit). if the adc input level is less than full- scale, bits p5-p0 represent the peak value from - 60 db to 0 db of full scale in 1 db steps. the psl outputs are accurate to within 0.25 db. bit p6 pro- vides a coarse means of determining an adc input idle condition. bit p7 indicates an adc overflow condition if the adc input level is greater than full-scale. p7 - overrange 0 - analog input less than full-scale level 1 - analog input greater than full-scale p6 - idle channel 0 - analog input >-60 db from full-scale 1 - analog input <-60 db from full-scale p5 to p0 - input level bits (1 db steps) inputs <0 db p5 - p0 0 db 000000 -1 db 000001 -2 db 000010 -60 db 111100 bar graph mode this mode provides a decoded output format which indicates the peak input signal level in a bar graph format which can be used to drive front panel leds. this decoded output can be used to drive front panel leds. input level t7 - t0 overflow 11111111 0 db to -3 db 01111111 -3 db to -6 db 00111111 -6 db to -10 db 00011111 -10 db to -20 db 00001111 -20 db to -30 db 00000111 -30 db to -40 db 00000011 -40 db to -60 db 00000001 < - 60 db 00000000 dual digital audio outputs the cs5396/97 contains two stereo digital audio output channels - sdata1 and sdata2. these audio output channels are completely independent, as sdata1 can contain 24-bit audio data simulta- neous with psychoacoustic audio data on sdata2. another example of this independence is 24-bit au- dio data output on sdata1 simultaneously with a low group delay output on sdata2. the audio output formats are completely program- mable through the i 2 c/spi c interface. the output
cs5396 cs5397 ds229pp2 19 formats include: inverted output, psychoacoustic output (16-bit, 18-bit, 20-bit), and low group delay output. psychoacoustic filter the cs5396/97 includes a programmable 10 tap digital filter which can be used to perform psycho- acoustic noise-shaping of the audio spectrum if desired. the filter can implement a variety of 16- bit, 18-bit, or 20-bit noise-shaped responses by setting the digital filter coefficients. further dis- cussion of the psychoacoustic filter can be found in appendix c. appendix b discusses an application using the psy- choacoustic filter independently of the a/d con- verter function. in this mode, sdata2 becomes an input to the psychoacoustic filter stage and sdata1 is the digital audio output. low group delay filter the characteristics of the low group delay filter are shown in figures 17 - 24. c interface formats the device supports either spi or i 2 c interface for- mats. the cs5396/97 monitors the state of cs dur- ing power-up and will configure to an spi interface if the pin is held low. conversely, if the pin is held high, the port will configure to a i 2 c interface. spi mode in spi mode, cs is the chip select signal, cclk is the c bit clock and cdin is the input data line from the microcontroller. notice that it is not pos- sible to read the cs5396/97 registers in spi mode due to the lack of a data output pin. to write to a register, bring cs low. the first 7 bits on cdin are the chip address, and must be zero. the eighth bit is a read/write indicator (r/w ) which must be low. the next 8 bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next 8 bits are the data which will be placed into the register designated by the map. the cs5396/97 has a map auto increment, which will increment the map after each byte is written, allowing block writes of successive registers. i 2 c mode in i 2 c mode, cdin is a bidirectional data line. data is clocked into and out of the part by cclk. the eighth bit of the address byte is the r/w bit (high for a read, low for a write). if the operation is a write, the next byte is the memory address point- er which selects the register to be read or written. if the operation is a read, the contents of the register pointed to by the memory address pointer will be output. map allows successive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. use of the i 2 c bus compatible in- terface requires a license from philips. i 2 c bus in a registered trademark of philips semiconductors. establishing the chip address in i 2 c mode connecting sdata1 pin and cs to 5 volts during power-up will set the device to the control port and i 2 c mode. however, the control port will not re- spond to cclk and cdata until the hold on the sdata1 pin is released. the chip address can be set by: 1) release the hold on the sdata1 pin of the de- vice to be addressed. 2) program the chip address and set the address enable bit, addren, which will prevent further communication to this device without the cor- rect address. 3) repeat steps 1 and 2 for the remaining devices on the bus. analog connections - all modes figure 1 shows the analog input connections. the analog inputs are presented differentially to the
cs5396 cs5397 20 ds229pp2 modulators via the ainr+/- and ainl+/- pins. each analog input will accept a maximum of 2.0 vpp. the + and - input signals are 180 out of phase resulting in a differential input voltage of 4.0 vpp. figure 8 shows the input signal levels for full scale. the analog modulator samples the input at 6.144 mhz (mclk=24.576 mhz) corresponding to fs equal to 48 khz in the 128 oversampling mode and fs equal to 96 khz in the 64 oversam- pling mode. the digital filter will reject signals within the stopband of the filter. however, there is no rejection for input signals which are (n 6.144 mhz) the digital passband frequency, where n=0,1,2,...a 39 w resistor in series with the analog input and a 6.8 nf cog capacitor between the inputs will attenuate any noise energy at 6.144 mhz, in addition to providing the optimum source impedance for the modulators. the use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoid- ed since these can degrade signal linearity. if active circuitry precedes the adc, it is recommended that the above rc filter is placed between the active cir- cuitry and the ainr and ainl pins. the above ex- ample frequencies scale linearly with output sample rate. the on-chip voltage reference and the common mode voltage are available at vref and vcom for the purpose of decoupling only. however, due to the sensitivity of this node, the circuit traces at- tached to these pins must be minimal in length and no load current may be taken from vref. it is pos- sible to use vcom as a reference voltage to bias the input buffer circuits, if the circuit trace is very short and vcom is buffered at the converter (refer to the CDB53965/97). the recommended decou- pling scheme for vref, figure 1, is a 470 f elec- trolytic capacitor and a 0.1 f ceramic capacitor connected from vref to agnd. the recommend- ed decoupling scheme for vcom, figure 1, is a 100 f electrolytic capacitor and a 0.1 f ceramic capacitor connected from vcom to agnd. grounding and power supply decoupling - all modes as with any high resolution converter, the adc re- quires careful attention to power supply and grounding arrangements if its potential perfor- mance is to be realized. figure 1 shows the recom- mended power arrangements, with va and vl connected to a clean +5 v supply. vd, which pow- ers the digital filter, should be run from the system +5 v logic supply, provided that it is not excessive- ly noisy (< 50 mv pk-to-pk). decoupling capaci- tors should be as near to the adc as possible, with the low value ceramic capacitor being the nearest. the printed circuit board layout should have sepa- rate analog and digital regions and ground planes, with the adc straddling the boundary. all signals, especially clocks, should be kept away from the vref pin in order to avoid unwanted coupling into the modulators. the vref decoupling capacitors, particularly the 0.01 m f, must be positioned to min- imize the electrical path from vref and pin 3, agnd. the CDB5396/97 evaluation board dem- onstrates the optimum layout and power supply ar- rangements, as well as allowing fast evaluation of the adc. to minimize digital noise, connect the adc digital outputs only to cmos inputs. +3.5 v +2.5 v +1.5 v +3.5 v +2.5 v +1.5 v cs5396/97 ain+ ain- full scale input level= (ain+) - (ain-)= 4.0 vpp figure 8. full scale input voltage
cs5396 cs5397 ds229pp2 21 digital filter plots figures 9-24 show the performance of the digital filters included in the adc. all plots are normal- ized to fs. assuming a sample rate of 48 khz, the 0.5 frequency point on the plot refers to 24 khz. the filter frequency response scales precisely with fs. magnitude (db) normalized frequency (fs) magnitude (db) normalized frequency (fs) figure 9. cs5396 stop band attenuation figure 10. cs5396 passband ripple magnitude (db) normalized frequency (fs) magnitude (db) normalized frequency (fs) figure 11. cs5396 transition band figure 12. cs5396 transition band
cs5396 cs5397 22 ds229pp2 magnitude (db) normalized frequency (fs) magnitude (db) normalized frequency (fs) figure 13. cs5397 stop band attenuation figure 14. cs5397 passband ripple magnitude (db) normalized frequency (fs) magnitude (db) normalized frequency (fs) figure 15. cs5397 transition band figure 16. cs5397 transition band
cs5396 cs5397 ds229pp2 23 magnitude (db) normalized frequency (fs) magnitude (db) normalized frequency (fs) figure 17. low group delay filter stop band attenuation 64x oversampling mode figure 18. low group delay filter passband ripple 64x oversampling mode magnitude (db) normalized frequency (fs) magnitude (db) normalized frequency (fs) figure 19. low group delay filter transition band 64x oversampling mode figure 20. low group delay filter transition band 64x oversampling mode
cs5396 cs5397 24 ds229pp2 figure 21. low group delay filter stop band attenuation 128x oversampling mode figure 22. low group delay filter passband ripple 128x oversampling mode figure 23. low group delay filter transition band 128x oversampling mode figure 24. low group delay filter transition band 128x oversampling mode
cs5396 cs5397 ds229pp2 25 register description ** default ==> bit status after power-up-sequence analog control (address 00000001) fstart (frame start)default = 0. this bit must be set to 1 to synchronize the modulator output and the decimation filter input and is automatically reset to 0 after a fstart pulse is sent to the analog and digital block. gndcal (ground calibration enable) default = 0. modulator input is tied to internal vcom when this bit is 1. aapd (analog section of modulator in power down) default = 0. the analog section of the modulator is in power down mode when aapd = 1. adpd (digital section of modulator in power down) default = 0. the digital section on the modulator is in power down mode when adpd = 1. test bit default =0. must remain at 0. mode (address 00000010) 128x/64x default = 0. oversampling ratio is 128 when this bit is 1 and 64 when this bit is 0. cal (system calibration enable) default = 0. setting this bit to 1 will initiate calibration. this bit is automatically reset to 0 following calibration. change_sign (change sign enable) default = 0. a 1 will interchange the analog input paths within each channel resulting in a phase inversion of the analog signal. this bit applies to both channels. _lr/ll (left-right output disable) default = 0. if this bit is 0, sdata1 will output the left and right channel data from the sdata1 source and sdata2 will output the left and right channel data from the sdata2 source as described else- where in the data sheet. if this bit is set to 1, the left channel data from sdata1 source and sdata2 source (stored in audio port register) will be sent out in sdata1. sdata2 will output all the right channel data. 76543210 fstart gndcal aapd adpd 1bit 00000 76 5 43210 128x/64x cal change_sign _lr/ll _hpen s/_m dfs mute 00 0 00000
cs5396 cs5397 26 ds229pp2 hpen (hp enable) default = 0. the highpass filter will be disabled when _hpen = 1. the highpass filter will be automatically enabled following calibration. s/_m (slave / master mode) default = 0. in master mode, lrck, and sclk are outputs. in slave mode, lrck and sclk are inputs. this bit is ignored when sdata1 is used as input port in fir2in or psychoin mode (refer to dig- ital control & tag register and appendix b). dfs (digital format select)default = 0. output of serial data complies with i 2 s standard when dfs is 1. out- put of serial data is left justified when dfs is 0. mute default = 0. data at sdata1 and sdata2 is always 0 when this set to 1. audio port (address 00000011) 24bit(sdata1) default = 1. a 1 enables the serial audio port 1 to transmit the 24-bit high precision output. this bit must be set to 0 to enable other sdata1 output options. 24bit(sdata2) default = 0. a 1 enables the serial audio port 2 to transmit 24-bit high precision output. this bit must be set to 0 to enable other sdata2 output options. psycho(sdata1) default = 0. psychoacoustic output will be the data at the serial audio port 1 if this bit is 1 and all other bits of the port are set to 0. psycho(sdata2) default = 0. psychoacoustic output will be the data at the serial audio port 2 if this bit is 1 and all other bits of the port are set to 0. psel18/_16(psycho 18bit or 16bit) default = 0. this bit indicates the number of output bit if the psychoacoustic filter is chosen as output. a 0 here allows 16 bits output whereas a 1 allows 18 bits output as long as psel20/_16 is 0. psel20/_16(psycho 20bit) default = 0. this bit has the highest priority when setting the number of output bit of psychoacoustic filter. if this bit is 1, the output is set to 20-bit regardless of the status of psel18/_16. lgd(sdata1) default = 0. 24-bit low-group-delay filter output will go through a highpass filter if _hpen bit in the mode register is 0. the lgd output will be the data at the serial audio port 1 if this bit is 1 and all other bits of the port set to 0. lgd(sdata2) default = 1. 76543210 24bit (sdata1) 24bit (sdata2) psycho (sdata1) psycho (sdata2) psel18/_16 psel20/_16 lgd (sdata1) lgd (sdata2) 10000001
cs5396 cs5397 ds229pp2 27 24-bit low-group-delay filter output will go through a high passfilter if _hpen bit in the mode register is 0. if _hpen is 1, data at the serial audio port will derive directly from the lgd filter output. if more than 1 bit is set for sdata2, low-group-delay filter output will be selected for output at the port. test mode 0(address 00000100) aoverflow a 1 indicates an overflow condition occurs in the modulator. this bit is reset by reading the register. doverflow a 1 indicates an overflow condition occurs in the decimation filter. this bit is reset by reading the register. fir1_en(sdata) default = 0. test purpose only. fir1l_r(fir1 l channel enable) default = 0. test purpose only. _psydither(psychoacoustic filter dither disable) default = 0. a 0 means adding dither in the psychoacoustic filter. dstart1, dstart2(dstart control bits) default = 00. test purpose only. test mode 1(add 00000101) for factory use only chip address (address 00000110) caddr(6-0) (chip address (bit6 to bit0)) default = 0000000. this is used to store the programmable chip address for i 2 c and spi mode. when more than 1 device are connected to the i 2 c or spi buses and using chip address is nec- essary, chip address set up is done by: 1) hold the sdata1 pin of every chip to 1 during power up. 76543210 aoverflow doverflow fir1_en fir1(lrck) _psydither dstart1 dstart0 0000000 76543210 test mode. reserved for factory use only 76543210 caddr6 caddr5 caddr4 caddr3 caddr2 caddr1 caddr0 0000000
cs5396 cs5397 28 ds229pp2 2) release the sdata1 pin of the chip that is going to be programmed with chip address. 3) send chip address and addren=1 (in register 7) through the serial control port. (the re- maining devices will not repond to this request.) 4) repeat step 2) and step 3) for to other chips one-by-one. (sdata1 output is tri-stated until it is released from pull up.) digital control & peak signal level (address 00000111) addren(chip address enable) default = 0. when this bit is 0, no chip address comparison is done. the chip will response to all the request from control port. when this bit is 1, the chip responds to the c only if the chip address from the c matches the chip address stored in caddr(6-0). pken(peak enable) default = 0. psl bits calculation is based on the high precision 24-bit output. psl bits output follows the serial audio port that sends out 24-bit data. if this bit is disabled, the psl bits location on the output stream will be replaced by zeros. pkupdate(peak update) default = 0. a 0 to 1 transition will load the peak value (since the last update) to the appropriate serial au- dio port. the internal peak register will then reset to 0. hr/_bg(peak display format) default = 0. high resolution tag format (hr/_bg=1) converts the 24-bit decimation filter output into 1 db step. bar graph tag format (hr/_bg=0) allows lcd display format of the 24-bit output with 8 discrete values. ddpd(digital filter power down enable) default = 0. the digital filter and serial audio port is in power down mode when ddpd = 1. fir2in(external fir2 input enable) default = 0. input of 2nd stage decimation filter is taken from the sdata2 port. the input data will be deci- mated by 2 and then output to sdata1 of serial audio port. psychoin (external psychoacoustic filter input enable) default = 0. input of psychoacoustic filter is taken from the sdata2 port. the 24-bit input data will be truncat- ed in psychoacoustic filter to the chosen output word length and then output to sdata1 of serial audio port. 76543210 addren pken pkupdate hr/_bg ddpd fir2in psychoin 0 000 000
cs5396 cs5397 ds229pp2 29 r_cal_coeff (address 00001000 - 00001010) default = 0000 0000 0000 0000 0100 0000. (represents 1) the right channel calibration factor is stored in these registers with msb in bit 7 of register ad- dress 00001010. this value is updated after every calibration cycle. user can read from or write to this calibration factor through the serial control port. l_cal_coeff (address 00001011 - 00001101) default = 0000 0000 0000 0000 0100 0000. (represents 1) the left channel calibration factor is stored in these registers with msb in bit 7 of register ad- dress 00001101. this value is updated after every calibration cycle. user can read from or write to this calibration factor through the serial control port. l_offset (address 00001110) default = 0000 0000. user can read or write this offset through the serial control port. r_offset (address 00001111) default = 0000 0000. user can read or write this offset through the serial control port. 76543210 ralpha (bit7) ralpha (bit6) ralpha (bit5) ralpha (bit4) ralpha (bit3) ralpha (bit2) ralpha (bit1) ralpha (bit0) 00000000 ralpha (bit15) ralpha (bit14) ralpha (bit13) ralpha (bit12) ralpha (bit11) ralpha (bit10) ralpha (bit9) ralpha (bit8) 00000000 ralpha (bit23) ralpha (bit22) ralpha (bit21) ralpha (bit20) ralpha (bit19) ralpha (bit18) ralpha (bit17) ralpha (bit16) 01000000 76543210 lalpha (bit7) lalpha (bit6) lalpha (bit5) lalpha (bit4) lalpha (bit3) lalpha (bit2) lalpha (bit1) lalpha (bit0) 00000000 lalpha (bit15) lalpha (bit14) lalpha (bit13) lalpha (bit12) lalpha (bit11) lalpha (bit10) lalpha (bit9) lalpha (bit8) 00000000 lalpha (bit23) lalpha (bit22) lalpha (bit21) lalpha (bit20) lalpha (bit19) lalpha (bit18) lalpha (bit17) lalpha (bit16) 01000000 76543210 los(bit13) los(bit12) los(bit11) los(bit10) los(bit9) los(bit8) los(bit7) los(bit6) 00000000 76543210 ros(bit13) ros(bit12) ros(bit11) ros(bit10) ros(bit9) ros(bit8) ros(bit7) ros(bit6) 00000000
cs5396 cs5397 30 ds229pp2 psycho coeff (address 00010000 - 00011000) h1 default = 1101 1010. h2 default = 0011 0101. h3 default = 1100 0010. h4 default = 0100 0011. h5 default = 1100 1011. h6 default = 0010 0011. h7 default = 1110 1100. h? default = 0000 1001. h8 default = 1111 1111. psychoacoustic filter coefficients. 2s complement representation. 4 msb bits represent left of binary point. 4 lsb represent right of binary point. user can read or write one or all of the coefficients through the serial control port. 76543210 pc8(bit8) pc8(bit7) pc0(bit5) pc8(bit4) pc8(bit3) pc8(bit2) pc8(bit1) pc8(bit0) 11011010 pc7(bit8) pc7(bit7) pc1(bit5) pc7(bit4) pc7(bit3) pc7(bit2) pc7(bit1) pc7(bit0) 00110101 pc6(bit8) pc6(bit7) pc2(bit5) pc6(bit4) pc6(bit3) pc6(bit2) pc6(bit1) pc6(bit0) 11000010 pc5(bit8) pc5(bit7) pc3(bit5) pc5(bit4) pc5(bit3) pc5(bit2) pc5(bit1) pc5(bit0) 01000011 pc4(bit8) pc4(bit7) pc4(bit5) pc4(bit4) pc4(bit3) pc4(bit2) pc4(bit1) pc4(bit0) 11001011 pc3(bit8) pc3(bit7) pc5(bit5) pc3(bit4) pc3(bit3) pc3(bit2) pc3(bit1) pc3(bit0) 00100011 pc2(bit8) pc2(bit7) pc6(bit5) pc2(bit4) pc2(bit3) pc2(bit2) pc2(bit1) pc2(bit0) 11101100 pc1(bit8) pc1(bit7) pc7(bit5) pc1(bit4) pc1(bit3) pc1(bit2) pc1(bit1) pc1(bit0) 00001001 pc0(bit8) pc0(bit7) pc8(bit5) pc0(bit4) pc0(bit3) pc0(bit2) pc0(bit1) pc0(bit0) 11111111
cs5396 cs5397 ds229pp2 31 pin descriptions power supply connections va - positive analog power, pin 24. positive analog supply. nominally +5 volts. vl - positive logic power, pin 23. positive logic supply for the analog section. nominally +5 volts. agnd - analog ground, pin 3, 25 and 28. analog ground reference. lgnd - logic ground, pin 22 ground for the logic portions of the analog section. vd - positive digital power, pin 11. positive supply for the digital section. nominally +5 volts. dgnd - digital ground, pin 12. digital ground for the digital section. analog inputs ainr-, ainr+ - differential right channel analog inputs, pin 26, 27. analog input connections for the right channel differential inputs. nominally 4.0 vpp differential for full-scale digital output.
cs5396 cs5397 32 ds229pp2 ainl-, ainl+ - differential left channel analog inputs, pin 4,5. analog input connections for the left channel differential inputs. nominally 4.0 vpp differential for full-scale digital output. analog outputs vcom - common mode voltage output, pin 2. nominally +2.5 volts. requires a 100 m f electrolytic capacitor in parallel with 0.1 m f ceramic capacitor for decoupling to agnd. caution is required if this output is to be used to bias the analog input buffer circuits. refer to text. vref - voltage reference output, pin 1. nominally +4.0 volts. requires a 470 m f electrolytic capacitor in parallel with 0.1 m f ceramic capacitor for decoupling to agnd. digital inputs adctl - analog control input, pin 6. must be connected to dactl. this signal enables communication between the analog and digital circuits. mclka - analog section input clock, pin 7. this clock is internally divided and controls the delta-sigma modulators. the required mclka frequency is determined by the desired output sample rate (fs). mclka of 24.576 mhz corresponds to an fs of 96 khz in 64 x oversampling mode and 48 khz in 128 x oversampling mode. mclkd - digital section input clock, pin 20. mclkd clocks the digital filter and must be connected to mclka. the required mclkd frequency is determined by the desired output sample rate (fs). mclkd of 24.576 mhz corresponds to an fs of 96 khz in 64 x oversampling mode and 48 khz in 128 x oversampling mode. digital input pin definitions for stand-alone mode dfs - digital format select, pin 18. the relationship between lrck, sclk and sdata is controlled by the dfs pin. when high, the serial output data format is i 2 s compatible. the serial data format is left-justified when low. pdn - power-down, pin 19. when high, the device enters power-down. upon returning low, the device enters normal operation. calibration of the device is required following release of power-down.
cs5396 cs5397 ds229pp2 33 s/m - slave or master mode, pin 17. when high, the device is configured for slave mode where lrck and sclk are inputs. the device is configured for master mode where lrck and sclk are outputs when s/m is low. cal - calibration, pin 10. activates the calibration of the tri-level delta-sigma modulator. digital pin definitions for control-port mode cdin - control port data input, pin 18. control port data input for spi mode. control port data input and output for i 2 c mode. cs - chip select input, pin 19. control port chip select for spi mode. the cs5396/97 monitors the state of cs during power- up and will configure to an spi interface if this pin is held low. conversely, if held high, the port will configure to a i 2 c interface. cclk - control port clock input, pin 17. control port clock input pin for both i 2 c and spi modes. cal - calibration, pin 10. cal pin is not functional in control port mode and should be connected to ground. digital outputs dactl- digital to analog control output, pin 9. must be connected to adctl. this signal enables communication from the digital circuits to the analog circuits. sdata1 - digital audio data output #1, pin 16. stand-alone mode - the 24-bit audio data is presented msb first, in 2's complement format. control port mode - the 24 audio data bits are presented msb first, in 2's complement format. the audio data can be followed by 8 peak signal level bits which indicate the peak signal level. the additional audio data options include; 16, 18, or 20-bit data with or without psychoacoustically optimized dither; or the output of the low group delay filter. the sdata1 output is completely independent from sdata2. the mode selection between stand-alone and control port mode is determined by the state of the sdata1 pin during power-up. a 47 k w pull-up resistor on sdata1 will select the control port mode. however, the control port will not response to cclk and cdin until the pull-up on the sdata1 pin is released.
cs5396 cs5397 34 ds229pp2 sdata2 - digital audio data output #2, pin 15. stand-alone mode - the 24-bit low group delay audio data is presented msb first, in 2's complement format. control port mode - the 24-bit low group delay audio data is presented msb first, in 2's complement format. the audio data can be followed by 8 peak detect bits which indicate the peak signal level. the additional audio data options include; the standard 24-bit word; 16, 18, or 20-bit data with or without psychoacoustically optimized dither. the sdata2 output is completely independent from sdata1. digital inputs or outputs lrck - left/right clock, pin 13. lrck determines which channel, left or right, is to be output on sdata1 and sdata2. in master mode, lrck is an output whose frequency is equal to fs. in slave mode, lrck is an input whose frequency must be equal to fs. although the outputs for each channel are transmitted at different times, left/right pairs represent simultaneously sampled analog inputs. stand-alone mode - the relationship between lrck, sclk and sdata is controlled by the digital format select (dfs) pin. control port mode - the relationship between lrck, sclk and sdata is controlled by the control register. sclk - serial data clock, pin 14. stand-alone mode - clocks the individual bits of the serial data from sdata1 and sdata2. in master mode, sclk is an output clock at 64 x fs. in slave mode, sclk is an input which requires a continuously supplied clock at any frequency from 48 x to 128 x fs (64 x is recommended). the relationship between lrck, sclk and sdata is controlled by the digital format select (dfs) pin. control port mode - clocks the individual bits of the serial data from sdata1 and sdata2. in master mode, sclk is an output clock at 128 x the output sample rate in the 128 x oversampling mode and 64 x the output sample rate in the 64 x oversampling mode. in slave mode, sclk is an input, which requires a continuously supplied clock at any frequency from 32 x to 128 x the output sample rate. a 128 x sclk is preferred in the 128 x oversampling mode and 64 x sclk is preferred in the 64 x oversampling mode. the relationship between lrck, sclk and sdata is controlled by the control register. miscellaneous tsto1, tsto2 - test outputs, pins 8 and 21. these pins are intended for factory test outputs. they must not be connected to any external component or any length of circuit trace.
cs5396 cs5397 ds229pp2 35 parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 hz to 20 khz), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale analog output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/ c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv.
cs5396 cs5397 36 ds229pp2 additional information 1) techniques to measure and maximize the per- formance of a 120 db, 24-bit, 96 khz a/d inte- grated circuit by steven harris, steven green and ka leung. paper presented at the 103rd convention of the audio engineering society, september 1997. 2) a 120 db dynamic range, 96 khz, 24-bit an- alog-to-digital converter by kafai leung, sa- rah zhu, ka leung and eric swanson. paper presented at the 102nd convention of the au- dio engineering society, march 1997. 3) a 5 v, 118 db delta sigma analog-to-digital converter for wideband digital audio by ka y. leung, eric j. swanson, kafai leung, sarah s. zhu. presented at isscc february, 1997, pa- per fp 13.6 4) how to achieve optimum performance from delta-sigma a/d and d/a converters by steven harris. presented at the 93rd conven- tion of the audio engineering society, october 1992. 5) the effects of sampling clock jitter on nyquist sampling analog-to-digital convert- ers, and on oversampling delta sigma adcs by steven harris. paper presented at the 87th convention of the audio engineering society, october 1989. 6) a fifth-order delta-sigma modulator with 110 db audio dynamic range by i. fujimori, k. hamashita and e.j. swanson. paper present- ed at the 93rd convention of the audio engi- neering society, october 1992. 7) an 18-bit dual-channel oversampling delta- sigma a/d converter, with 19-bit mono ap- plication example by clif sanchez. paper pre- sented at the 87th convention of the audio engineering society, october 1989. 8) a stereo 16-bit delta-sigma a/d converter for digital audio by d.r. welland, b.p. del signore, e.j. swanson, t. tanaka, k. hamash- ita, s. hara, k. takasuka. paper presented at the 85th convention of the audio engineering society, november 1988.
cs5396 cs5397 ds229pp2 37 package dimensions f e g h i a b d c l k j b bsc 1.27 0.050 bsc c nom 7 7 nom d 0.005 0.013 0.127 0.330 e 0.095 0.105 2.41 2.67 soic 28 pin millimeters inches min max max min dim nom 45 45 nom f nom 7 7 nom g 0.008 0.015 0.203 0.381 h 8 2 8 2 i 0.292 0.298 7.42 7.59 j 0.355 0.345 8.76 9.02 k 0.420 0.400 10.16 10.67 l a 0.710 0.690 17.53 18.03 m 0.020 0.013 0.33 0.51 m
cs5396 cs5397 38 ds229pp2xc appendix c: psychoacoustic filter the p sycho a c o ustic filt e r in t he cs5 3 96 is based o n the p ap e r: "r o bert a. wa n na m aker, psyc h oaco u s- tically optim a l n o ise sha p i n g, jo u r n a l of t h e audio engin e ering s o ciety, vol 40, no 7 /8, 1 992 j u ly/au- gust." the de f ault coef f icie n ts in th e cs 5 396 are t h e fir 9 -tap f ilter coef f icie n ts described in table 3 of the pa p er. since t he e ffective noise sha p ing fu n ctio n is (1-h), the cs 5 396 regis t ers save t he (1-h) f u nc- ti o n coe f fici e nts. th e r e fore , the n eg a tive o f e a ch filter co e ffici e nt is st o red in t h e re g isters. e a ch c o efficie n t is re p r e s e nted as a binary 2s complemen t number where t he 4 msbs re p resen t the w h ole number o f the coef f icie n t an d the 4 lsbs represen t the f r a c t i o nal portio n tr u nc a ted t o 4 bin a ry bi t s. def a ult co e ffici e nts as listed in "r o bert a. w an n am a k e r, psyc h oacoustic a ll y o p ti m a l nois e s h aping a1 = 2 .412 a2 = -3 . 370 a3 = 3 .937 a4 = -4 . 174 a5 = 3 .353 a6 = -2 . 205 a7 = 1 .281 a8 = -0 . 569 a9 = 0 .08 4 7 c o eff i c i e n t c o n v e r s i o n e x a m p l e 1 : a1 = 2 .412 a 1 = (0 0 10. 0 11 0 ) binary r e pese n tatio n with the fracti o nal portio n tr u ncated t o 4 bits. -a1 = -(001 0 .0 1 10) b in a ry re p r e s e ntation -a1 = 1 1 01. 1 010 in tw o s com p le m ent this value is stored i n r e gist e r 1 0h. c o eff i c i e n t c o n v e r s i o n e x a m p l e 2 : a2 = -3 . 370 -a2 = 3 . 370 -a2 = 0 0 11. 0 101 b in a ry re p esent a ti o n with t he fraction a l p orti o n tru n c a te d to 4 bi t s. -a2 = 0 011 . 01 0 1 in 2 's co m pl e me n t this value is stored i n r e gist e r 1 1h.
cs5396 cs5397 d s2 2 9pp2 x c 3 9 psycho - acoustic filter coe f ficients access: r/w in i2c and write only i n spi filter coefficient a1 (address 10h) filter coefficient a2 (address 11h) filter coefficient a3 (address 12h) filter coefficient a4 (address 13h) filter coefficient a5 (address 14h) filter coefficient a6 (address 15h) filter coefficient a7 (address 16h) filter coefficient a8 (address 17h) filter coefficient a9 (address 18h) default: a 1 - 1 101 10 1 0 a 2 - 0 011 01 0 1 a 3 - 1 100 00 1 0 a 4 - 0 100 00 1 1 a 5 - 1 100 10 1 1 a 6 - 0 010 00 1 1 a 7 - 1 110 11 0 0 a 8 - 0 000 10 0 1 a 9 - 1 111 11 1 1 76 5 432 1 0 m sb b i t 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb
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